1. Field of the Invention
The present invention relates to a method and apparatus for converting an input signal to an output signal at a high rate of speed, and, more particularly, to a method and apparatus for accessing values in a memory device at high rates of speed.
2. Description of Related Art
In the field of information processing it is highly desirable to convert or transform a signal from one form to another at a high rate of speed. A signal is often represented by a stream of data and arrives at an input to the information processing system. Each datum in the stream often arrives at the input at a fixed time period after the preceding datum has arrived. The shorter the period is between incoming data, the higher the rate is of the data stream.
The data stream can also be considered as a time sequence of values arriving at the input to the information processing device. When a stream of incoming data arrives at an input to an information processing system at a high rate, it is often advantageous to convert or transform that data to an output at an equally high rate. Usually, at least one output stream of data is desired at a rate substantially equal to the input rate.
One example of a system wherein high conversion rates are desired is in a colorenhancement system for conventional video displays. The image on the video display is composed of many points known as pixels. Each pixel is displayed according to data indicating its position on the display screen and the color to be displayed at that position. The image is composed by updating the display screen frequently using data provided for each pixel. Color-enhancement usually is accomplished by expanding the number of bits used to designate color data for each pixel.
In many conventional video display systems, pixel color data is composed of 8-bits of digital information, which allow for the potential to display 256 different colors at that pixel position. In order to enhance the quality of the displayed image, a practice has developed of expanding, in a conversion or transformation, the number of pixel color data bits, to, for example, 18 or 24 bits per pixel. Although such a practice results in an enhanced color image, difficulties and limitations are encountered in its implementation.
A significant limitation is that the conversion device requires a relatively long amount of time to effect a conversion, or, in this case, a bit-length expansion. This has required the makers of color enhancement systems to limit the rate of the incoming color pixel data stream to accommodate a slow conversion device. Slowing down the data stream means that the pixel information in the video display cannot be sent to the display screen as frequently, thereby limiting the image quality.
One of the most commonly used types of conversion devices is a Random Access Memory (RAM). In a RAM, data values are stored in a number of locations commonly referred to as addresses. Each address or location holds one data value. An input signal to the RAM, commonly referred to as an address signal, indicates which data value will be made available by the RAM on its output line as an output signal. The RAM effects a conversion by accepting an address input value, pointing to or selecting a stored data value in a memory location based on the address input value, and by outputting the data value stored in the selected memory location. The time it takes for the RAM to convert an address input to a valid data signal value is usually referred to as an access time.
Returning to the video display example, one color-enhancement scheme makes use of a RAM with an 8-bit address input capable of addressing or pointing to 256 (2.sup.8) separate memory locations. The RAM can be built to store and output data values having virtually any bit-length, such as 18 or 24 bits. By storing appropriate data values in each memory location, the RAM is capable of converting 8-bits of input data to, for example, 18 or 24 bits of output data. Ordinarily, a conventional video display is configured to accept 8-bits of incoming color data per pixel in a data stream. The video display can be reconfigured to accept an expanded number of bits, such as 18 or 24, in an incoming data stream. A RAM is interposed between the video display and the incoming 8-bit data stream so that the incoming 8-bit data stream becomes an address input to the RAM. The address input is used to access an appropriate expanded value, stored in a memory location or address, and to use that value as output to the video display.
Hence, the video display accepts more color information per pixel, increasing the image quality of the displayed image. However, the period between incoming data values in the data stream must not exceed the access time of the RAM, or erroneous conversions will occur, scrambling the image. In other words, the rate of incoming data must be decreased to accommodate the RAM access time to maintain image integrity. This limits the quality of the image capable of being displayed by the video display.
The display of a video image is just one example of an information processing application which requires a conversion of a signal from one form to another at a high rate of speed. Many other situations are encountered where a conversion device, such as a RAM, requires a conversion time which exceeds the potential period between incoming data in a data stream, so that accurate conversion is not possible without slowing down the incoming data stream. A common solution in such situations has been to slow down the data stream to accommodate a slow conversion device.
Various references discuss the rate of image generation in a video display device. However, the general problem of having to accommodate a relatively slow access device has not been adequately resolved by these references.
For example, U.S. Pat. No. 4,905,189, issued to Brunolli, discloses a system for synchronously reading information from a RAM device on a fast port independently of the devices ability to asynchronously read or write information to the RAM on a slow port. Information is read out of the memory and evaluated using two alternatingly switched channels to increase the evaluation speed.
This reference does not effectively address the problem of converting values in an incoming data stream at a relatively high rate using a conversion device having a high conversion or access time, utilizing external timing control elements. It merely teaches how to increase the evaluation speed of data after it has been read out of the device.
Another example, U.S. Pat. No. 4,742,350, issued to Ko et al., discloses a system for displaying an image using picture data, attribute data, and synchronization data, wherein the attribute data includes embedded synchronization data.
U.S. Pat. No. 4,791,589, issued to Sherrill et al., discloses multiple color map memories to quickly store color map information during display line retrace intervals. This primarily involves a scheme for quickly writing data into multiple color map RAM memories, included in a display processor, from a video RAM (VRAM) memory.
U.S. Pat. No. 5,163,024, issued to Heilveil et al., discloses a video memory device employing a bit-mapped RAM unit, a serial shift register and appropriate decode circuitry to enable a single video memory to be used with displays using various numbers of bit resolution.
Although teaching the principles of data storage and retrieval in a random access memory, the prior art, as represented by these references, does not effectively address the problem of converting values in a data stream at a relatively high rate using a conversion device having a high conversion time.